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Core1553BRT v4.0 Handbook
Table 6-3 ? Verification Testbench Menu Summary
Menu Command
Quick Run
Microsemi Tests
Standard Mode
RT Test Plan
Do Everything
Action
Runs a few simple 1553B command sequences to demonstrate that the
core is functioning.
– Runs the complete set of Microsemi verification tests. For the RTL code
( verif_rtl directory), this takes several hours, depending on the computer
used. For the Obfuscated version, the simulation time is significantly
longer.
This implements a subset of the protocol tests specified in the MIL-HDBK-
1553A handbook. This takes a very long time to run, as thousands of
1553B command words need to be transmitted and verified.
This runs the three options listed above, i.e., Quick, Microsemi, and Test
Plan.
Microsemi Tests – This runs the Standard Mode tests but uses an address mapping function
Address Mapper Enabled
(as on 57 ).
Microsemi Tests – Short This runs a subset of the Standard Mode tests; the runtime is much shorter
Mode
Do Everything and Quit
RAM Monitors
Bus Monitors
Pause Simulation
Run 1553B Word
Send a Message
Set RT Memory
Display RT Memory
than for the standard tests.
This runs the three options in Do Everything above and then quits the
simulation. Setting the RUNTEST generic to 9 can automatically run this
test option.
The testbench can display a message every time the backend RAMs are
written to or read from. This option enables or disables the RAM monitors.
When enabled, the testbench runs more slowly due to the printing
overhead in VHDL.
The testbench includes 1553B bus monitors that display every word
transmitted on the 1553B busses. This option enables or disables the bus
monitors. When enabled, the testbench will run slower due to the printing
overhead in VHDL.
Exits the simulation and returns to the vsim environment. This may be
required to cause the waves window to update. Simulation can be simply
restarted using the run -all command.
Simply allows the simulation to run for 20 μs.
Allows interactive 1553B message creation.
Allows the values in one of the RT memories to be set.
Displays the contents of one of the RT memories.
Revision 3
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